Receiver architecture with digitally generated intermediate frequency

ABSTRACT

A receiver can be configured to include an RF front end that is configured to downconvert a received signal to a baseband signal or a low Intermediate Frequency (IF) signal. The receiver can downconvert the desired signal from an RF frequency in the presence of numerous interference sources to a baseband or low IF signal for filtering and channel selection. The filtered baseband or low IF signal can be converted to a digital representation. The digital representation of the signal can be upconverted in the digital domain to a programmable IF frequency. The digital IF signal can be converted to an analog IF signal that can be processed by legacy hardware.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.60/618,240, filed Oct. 12, 2004, entitled A RECEIVER ARCHITECTURE WITHDIGITALLY GENERATED INTERMEDIATE FREQUENCY; which is hereby incorporatedherein by reference in its entirety.

BACKGROUND

The disclosure relates to electronic signal processing. Moreparticularly, the disclosure relates to an RF receiver and receiverarchitecture.

In a typical frequency division multiplex communication system, multipletransmissions can simultaneously occupy a predefined operating band. Thesignals within the operating band can operate according to apredetermined communication standard, and thus, can have an energywithin a predictable dynamic range. The communication standard can alsospecify a frequency spacing between adjacent channels, and the channelbandwidth. The communication standard can also specify signalparameters, such as modulation type, information rates, out of channelperformance, as well as other signal parameters.

Additionally, there can be numerous signal sources operating outside ofthe operating band. Unlike the signals within the operating band, theout of band signals are typically not regulated by the communicationstandard regulating the in band signal performance. As a result, out ofband signals may have substantially greater energy relative to thein-band signals, and can operate according to different signalparameters, including modulation type, out of band performance, andother parameters.

In order to tune to a desired channel, a receiver needs to substantiallyeliminate the effects of undesired channels, including those knowninterferers occurring within known operating bands as well asunanticipated interferers.

Many receiver implementations have been developed to support the variouscommunication standards. The trend of increasing device complexity andperformance while simultaneously reducing the physical size ofelectronic devices imposes tremendous constraints on ongoingdevelopment.

For example, the size of cellular and cordless telephones continues toshrink while simultaneously improving the quality of the device andadding additional functionality to the device. Similarly, radios andtelevisions are constantly being redesigned to provide improved featuresand operating modes while simultaneously decreasing physical size.Although the screen size available in television receivers continues togrow, the advancement of technologies that enable flat screens and shortdepths greatly reduce the volume available for electronics.

It is desirable to increase the ability of a receiver to operate inmultiple modes or frequency bands without compromising received signalquality. Additionally, it is desirable for a receiver implementation tominimize size, cost, and power consumption over implementationspresently available.

BRIEF SUMMARY

A receiver can be configured to include an RF front end that isconfigured to downconvert a received signal to a baseband signal or alow Intermediate Frequency (IF) signal. The receiver can downconvert thedesired signal from an RF frequency in the presence of numerousinterference sources to a baseband or low IF signal for filtering andchannel selection. The filtered baseband or low IF signal can beconverted to a digital representation. The digital representation of thesignal can be upconverted in the digital domain to a programmable IFfrequency. The digital IF signal can be converted to an analog IF signalthat can be processed by legacy hardware.

The disclosure includes a receiver that includes a downconverterconfigured to downconvert an input signal to a signal in a firstfrequency band, an analog to digital converter (ADC) coupled to thedownconverter and configured to digitize the signal in the firstfrequency band to produce a digital representation of the signal in thefirst frequency band, and a digital upconverter configured to upconvertthe digital representation of the signal in the first frequency band toa digital representation of the signal in a second frequency band.

The disclosure includes a receiver that includes a first frequencyconverter configured to downconvert a received signal to an in-phasebaseband signal component, a second frequency converter configured todownconvert the received signal to a quadrature baseband signalcomponent, a first analog filter coupled to the first frequencyconverter and configured to perform at least partial channel selectionon the in-phase baseband signal component, a second analog filtercoupled to the second frequency converter and configured to perform atleast partial channel selection on the quadrature baseband signalcomponent, a first Analog to Digital Converter (ADC) coupled to thefirst analog filter and configured to convert the in-phase basebandsignal component to a digital in-phase baseband signal component, asecond ADC coupled to the second analog filter and configured to convertthe quadrature baseband signal component to a digital quadraturebaseband signal component, a first digital filter coupled to the firstADC and configured to digitally filter the digital in-phase basebandsignal component to generate a digitally filtered in-phase basebandsignal component, a second digital filter coupled to the second ADC andconfigured to digitally filter the digital quadrature baseband signalcomponent to generate a digitally filtered quadrature baseband signalcomponent, a first digital upconverter configured to digitally upconvertthe digitally filtered in-phase baseband signal component to an in-phaseIntermediate Frequency (IF) signal component at a desired IF, a seconddigital upconverter configured to digitally upconvert the digitallyfiltered quadrature baseband signal component to a quadrature IF signalcomponent at the desired IF, and a digital signal combiner configured tocombine the in-phase IF signal component with the quadrature IF signalcomponent.

The disclosure includes a method of receiving a signal that includesfrequency converting an input signal to an intermediate signal in afirst frequency band, digitizing the intermediate signal, and digitallyconverting the intermediate signal to a second frequency band.

The disclosure includes a method of calibrating a quadrature receiver.The method includes injecting a calibration tone to a signal path of aquadrature receiver, detecting an amplitude and phase imbalance of thequadrature receiver, adjusting a gain of at least one of an in-phase anda quadrature signal path based on the amplitude imbalance, and adjustinga phase of at least one of the in-phase and quadrature signal pathsbased on the phase imbalance.

The disclosure includes a quadrature receiver calibration apparatus,that includes a tone generator configured to generate a calibrationtone, a coupler configured to couple the calibration tone to a signalpath of the quadrature receiver, a detector configured to detect anin-phase and quadrature signal component when the calibration tone iscoupled to the signal path, a gain feedback module configured to adjusta gain of at least one of an in-phase signal path and a quadraturesignal path, and a phase feedback module configured to adjust a phase ofat least one of the in-phase signal path and the quadrature signal path.

BRIEF DESCRIPTION OF THE DRAWINGS

The features, objects, and advantages of embodiments of the disclosurewill become more apparent from the detailed description set forth belowwhen taken in conjunction with the drawings, in which like elements bearlike reference numerals.

FIG. 1 is a simplified functional block diagram of an embodiment of areceiver in a system.

FIG. 2 is simplified functional block diagram of an embodiment of areceiver.

FIG. 3 is a simplified functional block diagram of an embodiment of areceiver with digital frequency conversion.

FIG. 4 is a simplified functional block diagram of an embodiment of areceiver with I/Q imbalance calibration.

FIG. 5 is a simplified functional block diagram of an embodiment of areceiver with I/Q imbalance calibration.

FIG. 6 is a simplified flowchart of a method of receiving signals.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

A receiver architecture is disclosed where the receiver performsconversion to zero Intermediate Frequency (IF) or low IF, performsanti-aliasing and partial channel selection filtering, converts thezero- or low-IF signal to the digital domain, performs frequencyconversion by digital processing (for example mixing) to an arbitraryintermediate frequency, then converts the signal back to the analogdomain with a digital-to-analog converter.

This approach provides the receiver with the following key advantages:an architecture suitable for single-chip implementation; flexiblechannel selection and IF filtering compatible with analog and digitalstandards; hybrid operation allowing a choice of either a low-IF ordirect conversion; flexible choice of IF; substantially perfectconversion of In-phase and Quadrature signal paths to the IF as a resultof the digital implementation; the option to perform digitalbaseband/low-IF processing; and an analog output that can be used by awide variety of existing demodulator processors.

The disclosed receiver is configured to select a relatively narrow-bandsignal (the desired “channel”) from among many undesired channels(“interferers”), filter out the interferers, and convert the desiredchannel to an arbitrary IF compatible with existing demodulators, whileintroducing minimal spurious signals, distortion and noise.

The receiver is configured to perform a low-IF or zero-IF conversion,which allows relatively low-power, efficient filtering to take place atthe baseband or low IF. The downconverted signal is digitized. Thistakes advantage of natural anti-aliasing performed by any channelselection, while enabling digital signal processing downstream.

The receiver the performs upconversion in the digital domain to adesired IF. Digital upconversion allows the process to be performed withsubstantially no mismatches in the I and Q path, eliminatingsubstantially all IF feedthrough and poor complex image rejection. Theresulting digital IF signal can be converted to the analog domain andfiltered using an on-chip anti-aliasing filter at the IF. This allowsgenerating an analog IF signal compatible with a range of existingdemodulators.

The receiver can be implemented by joining a zero- or low-IF receiverwith a digital baseband portion, a digital IF generator, and a digitalimplementation of a transmitter where the output signal is convertedback to the analog domain. The receiver architecture is particularlyadvantageous because the typical desired output intermediate frequencyis at a sufficiently low frequency to allow data conversion to beperformed by relatively low-power, low-complexity circuits.

FIG. 1 is a simplified functional block diagram of an embodiment of areceiver 100 implementing digital IF generation in a system 10. Thefollowing description describes an embodiment in which the system 10 isconfigured to operate as a television receiver. However, the system 10can be any of a plurality of systems. For example, the system 10 can bea television, television receiver, set top box, or television tunerintegrated within a video recorder or some other television receiver. Inother embodiments, the system 10 can be a radio receiver, wirelesstransceiver, telephone receiver, cellular telephone, cordless telephone,or some other communication device.

The system 10 can include a source switch 12 that can be coupled to oneor more signal sources. For example, a first source input can be coupledto an antenna 2 and a second source input can be coupled to a wiredsource, such as a cable coupled to a cable television distributor. Thesource switch 12 is not limited to coupling only one type of signal tothe receiver 100. For example, the source switch 12 can be coupled to atelevision signal source, for example, via the antenna 2, and can becoupled to a radio source, for example, via the cable 4.

The source switch 12 can be configured to couple any one of the signalsfrom any signal source to the input of the receiver 100. The receiver100 can be, for example, configured to selectively process televisionsignals received from a signal source, such as analog television signalsformatted according to an analog television standard, such as NTSC, PAL,SECAM, or some other analog television standard. The receiver 100 canalso be configured to process digital television signals, such asdigital DVB-T television signals, received from one of the signalsources.

The receiver 100 can receive the RF signal from the source switch 12 andcan downconvert the signal to an output IF. The output IF from thereceiver 100 can be coupled to a demodulator 50 and from the demodulator50 to a baseband processor 60. In one embodiment, the demodulator 50 canbe configured to demodulate a television signal at a predetermined IF.The demodulated television signals are communicated to a basebandprocessor 60 that can be configured, for example, to format the signalsinto video and audio signals for corresponding video and audio outputdevices (not shown).

The system 10 can also include a mode selection module 20 that can beconfigured to receive a mode selection input from an external source(not shown) that can be, for example, a user selection or user control.The mode can correspond to an operating mode of the receiver 100, andcan be used to determine a particular operating band, channel spacing,channel bandwidths, and output IF frequency.

The mode select module 20 can be coupled to a channel select module 30.The channel select module 30 can be coupled to the mode select module 20and can be configured to generate the desired local oscillator (LO)control signals. The channel select module 30 can generate the controlsignals needed to tune the LO frequencies of the receiver 100 to enablereception of the desired RF signal and generation of the desired outputIF. The channel select module 30 can also receive one or more inputsignals from an external source (not shown), such as a user interface orsome other module or device that can indicate a desired channelselection.

The channel select module 30 can independently control the RF and IF LOswithin the receiver 100. For example, the channel select module 30 cantune the RF LO to a frequency that is based on both a mode and a desiredchannel. The channel select module 30 can also be configured to controlthe frequency of the IF LO and may be configured to control the IF LObased only on the desired mode. In other embodiments, the channel selectmodule 30 can be configured to tune both the RF and LO frequencies foreach channel.

The channel select module 30 can also be configured to controlcalibration of the receiver 100. The calibration can include DC offsetcalibration and In-phase (I) and Quadrature (Q) signal balancing. Forexample, the channel select module 30 can control an RF switch withinthe receiver 100 and can initiate the DC offset calibration. In anotherembodiment, a calibration module within the receiver 100 can receive thechannel select signals and the filter control signals and can initiateDC offset calibration, including controlling the RF switch and filterbandwidths during the duration of the DC offset calibration.

A filter controller 40 can also be coupled to the mode select module 20.The filter controller 40 can be configured to provide the controlsignals to the receiver 100 that control one or more filter bandwidthswithin the receiver 100. The filter controller 40 can be configured toset the filter bandwidths based on the channel selectivity required inthe receiver 100, which can depend on the operating mode.

The filter controller 40 can also be in communication with the channelselect module 30. The filter controller 40 can be configured to controlthe filters within the receiver 100 to predetermined bandwidths for apredetermined calibration duration following each channel change. Forexample, the filter controller 40 can be configured to tune the filtersto a minimal bandwidth during DC offset calibration. Alternatively, acalibration module within the receiver 100 can be configured to controlthe filter bandwidths during the calibration duration.

A processor 72 and associated memory 74 can be included within thesystem 10 and can be configured to perform one or more functions withineach of the modules. For example, the memory 74 can include one or moreprocessor 72 usable instructions in the form of software that can, whenexecuted by the processor 72, perform some or all of the functions ofthe various modules within the system 10.

FIG. 2 is a simplified functional block diagram of an embodiment of areceiver 100 that can be implemented on one or more substrates of one ormore integrated circuits (ICs). In some embodiments, it may beadvantageous to integrate the entire receiver on a single IC. In otherembodiments, it may be advantageous to integrate a portion of thereceiver 100 in a first IC or on a first substrate and integrate theremainder of the receiver 100 on a second IC or second substrate. Thefirst and second substrates can be implemented in a single package ormay be implemented in distinct packages. For example, a signal pathwithin the receiver 100 can be implemented on a first substrate and oneor more local oscillators can be implemented on a second substrate andcouple to the first substrate through one or more interconnects.

Although the signal interconnections shown in FIG. 2 appear as singleended signal interconnects, it is generally understood that some or allof the interconnections can be implemented as differential connections.It may be advantageous to implement differential interconnections, forexample, for the purposes of noise reduction.

Portions of the receiver 100 can be implemented digitally, and can beconfigured to operate on digital representations of the signal. Thedigital processing of the signals within the receiver 100, andembodiments of receivers 100 having digital portions, are described infurther detail in subsequent figures. The embodiment of FIG. 2 does notexplicitly illustrate the digital portions to allow the description tofocus on the functionality of the various blocks and modules.

The receiver 100 can include an RF amplifier 102 that is configured toreceive a signal at the input to the receiver 100 and amplify it. The RFamplifier 102 can be configured to receive a signal, for example, froman interconnect to an antenna or wired connection, such as a singleended wireline, a differential wireline, a twisted pair, a coaxialcable, a transmission line, a waveguide, an optical receiver configuredto receive an optical signal over an optical fiber, and the like, orsome other signal medium.

The RF amplifier 102 can be configured in any of several differentembodiments or combination of embodiments, depending on the application.In one embodiment, the RF amplifier 102 can be a Low Noise Amplifier(LNA). In another embodiment, the RF amplifier 102 can be a variablegain amplifier, and the gain of the RF amplifier can be selected by oneor more control lines (not shown) to the receiver 100. In the embodimentwhere the RF amplifier 102 is a variable gain amplifier, the gain of theRF amplifier 102 can be part of a gain control loop, such as anautomatic gain control (AGC) loop (not shown). The RF amplifier 102 canbe configured as a single amplifier stage or can include multipleamplifier stages. Where multiple amplifier stages are used, theamplifier stages can include serial, parallel, or a combination ofserial and parallel amplifier configurations.

The output of the RF amplifier 102 can be coupled to inputs of first andsecond frequency conversion modules, here shown as a first mixer 112 anda second mixer 114. The first and second mixers 112 and 114 are shown asmixers, but can be any type of frequency conversion device. For example,the first and second mixers 112 and 114 can be double balanced mixers,double-quadrature mixers, harmonic reject mixers, interferometers, orsome other type of frequency conversion device. The first and secondmixers 112 and 114 can be configured to generate in-phase (I) andquadrature (Q) frequency converted signal components. The first mixer112 is described as part of the in-phase signal path and the secondmixer 114 is described as part of the quadrature signal path forpurposes of discussion.

An RF LO 120 can be configured to generate a local oscillator signal tofrequency convert the received RF signal to a baseband signal or a lowIntermediate Frequency (IF) signal. As used herein, the term basebandsignal refers to baseband signals as well as to signals that aresubstantially baseband signals. A signal is substantially a basebandsignal if the frequency conversion process to downconvert a signal isimperfect, for example, due to LO offset errors or differences at thetransmitter or receiver and errors or differences in the RF signalrelative to a specified frequency of operation. For example, an RFsignal may be different from a specified operating channel due to LOfrequency shifts at the transmitter or Doppler shifts. Typically, theerror or difference is a fraction of the baseband signal bandwidth.

A low IF signal can refer to an IF frequency that is less than twice thebaseband signal bandwidth. However, in other embodiments, low IF canrefer to less than 1.5, 2.5, 3, 4, 5, 10, or some other multiple of thebaseband signal bandwidth. Typically, a low IF signal refers to a signalthat is at a frequency sufficiently low to allow processing of thesignal without additional frequency conversions.

The receiver 100 can be configured to operate using direct conversion tobaseband in some operating modes while converting to a low IF in otheroperating modes. For example, the receiver 100 can operate in low-IFmode for analog TV applications, and zero-IF for digital applications.Using distinct frequency conversion modes for separate operating modesmay be advantageous because the receiver 100 architecture can beoptimized for signal characteristics.

Analog television standards such as NTSC or PAL require less channelselection and image rejection in its low-pass filtering, but are muchmore sensitive to DC offset which typically are present in a zero-IFimplementation. This makes an analog television receiver 100 more suitedfor a low-IF implementation, which may suffer from poorer channelselectivity, but which also substantially eliminates the DC offsetproblems associated with zero-IF.

Digital TV (e.g. DVB-T) requires greater channel selection, but is lesssensitive to DC offset that may be introduced by a zero-IF architecture.This makes digital TV well-suited for a zero-IF approach, which offersbetter channel selectivity and no image rejection limitations, but mayintroduce some DC offset to the signal.

The frequency of the RF LO 120 can be programmable, and the frequencycan be programmed based in part on the frequency of the desired signal.In a direct conversion frequency conversion, the output of the RF LO 120can be substantially equal to the center frequency of a double side bandinput signal. In other embodiments, the RF LO 120 can be tuned to afrequency that is a multiple of the desired input frequency. In theembodiment of FIG. 2, the RF LO 120 can be tuned to a frequency that issubstantially four times the frequency of the desired signal.

The output of the RF LO 120 can be coupled to a first phase shifter 122that can be configured to generate at least two distinct versions of aLO signal that are in quadrature. Because inaccuracies in the quadratureLO signals can contribute to undesired signal components in therecovered signal, it is desirable to generate accurate quadrature LOsignals. In one embodiment, the first phase shifter 122 can include aphase shifted signal path and a direct signal path, where the phaseshifted signal path results in a signal that is substantially 90 degreesshifted relative to the signal from the direct signal path. In anotherembodiment, the first phase shifter 122 can include a polyphase filterthat is configured to generate the two LO signals in quadrature. In theembodiment shown in FIG. 2, the first phase shifter can be implementedwithin the divide by four scaler.

The in-phase LO signal can be coupled to an in-phase LO buffer amplifier116 that amplifies the in-phase LO signal and couples it to a LO inputport of the first mixer 112. Similarly, the quadrature LO signal can becoupled to a quadrature LO buffer amplifier 118 that amplifies thequadrature LO signal and couples it to a LO port of the second mixer114.

The output of the first mixer 112 can be an in-phase baseband signalthat is coupled to an in-phase filter 132. The in-phase filter 132 canbe programmable filter whose bandwidth can be selected based on one ormore control signals (not shown) provided to the receiver 100. Thebandwidth of the in-phase filter 132 can be selected, for example, basedon a communication standard or mode that the receiver 100 is configuredto support. Therefore, where the receiver 100 is configured to supportmultiple standards having different channel bandwidths, the bandwidth ofthe in-phase filter 132 can be selected based in part on the presentlysupported mode.

When the signal is a baseband signal or a low IF signal, the in-phasefilter 132 can be configured as a low pass filter. Alternatively, thein-phase filter 132 can be configured as a bandpass filter if the low IFsignal has sufficient bandwidth to make the use of a low pass filterundesirable.

The output of the in-phase filter 132 can be coupled to a third mixer152 configured to frequency convert the in-phase signal to a desiredoutput IF. In one embodiment, the output of the in-phase filter 132 is abaseband signal and the third mixer is configured to upconvert thein-phase baseband signal to an output IF.

The third mixer 152 can be driven by a programmable LO that is generatedin much the same manner that is used to generate the LO for the firstand second mixers 112 and 114. A programmable IF LO 140 can beconfigured to generate a signal that is substantially four times thedesired output IF. The IF LO 140 can be programmable to allow the outputIF to be selected based in part on the mode supported by the receiver100. For example, the receiver 100 can be configured to frequencyconvert the input signals to a predetermined IF that can depend on themanner in which the user configures the system having the receiver 100.For example, a set top box for television signals can be configured togenerate an output signal at a predetermined IF, such as 70 MHz, or at afrequency corresponding to a television channel.

The output of the IF LO 140 can be coupled to a second phase shifter 142that can be implemented in a divide by four circuit. An in-phase LOoutput from the second phase shifter 142 can be coupled to an in-phasebuffer amplifier 156 that amplifies the in-phase LO signal and couplesit to the LO input of the third mixer 152. The output of the third mixer152 is an in-phase IF signal that is coupled to a first input of asignal combiner 160.

The quadrature signal path is configured to be substantially identicalto the in-phase signal path. The two signal paths are typicallysubstantially matched to reduce undesirable signal components that canbe generated due to I and Q mismatches.

The output of the second mixer 114 can be a baseband quadrature signalthat is coupled to an input of a quadrature filter 134. The quadraturefilter 134 can be configured as a programmable low pass filter havingprogrammable bandwidth. Typically, the configuration and bandwidths ofthe in-phase and quadrature filters 132 and 134 are the same such thatthe in-phase and quadrature signal paths remain substantially matched.

The output of the quadrature filter 134 can be coupled to an input of afourth mixer 154 that is configured to upconvert the quadrature signalto the output IF. The fourth mixer 154 is driven by an LO signal that isgenerated by the IF LO 140. The output of the IF LO 140 is coupled to asecond phase shifter 142 that generates a quadrature LO signal. Thequadrature LO signal is coupled to a quadrature buffer amplifier 158which amplifies the quadrature LO signal and couples it to an LO inputof the fourth mixer 154. The output of the fourth mixer 154 can be aquadrature IF signal. The quadrature IF signal can be coupled to asecond input of the signal combiner 160.

The signal combiner 160 can be configured to combine the in-phase andquadrature IF signals. The signal combiner 160 can be, for example, asignal summer that sums the in-phase IF signal with the quadrature IFsignal. In one embodiment, the signal combiner 160 sums the two signalsmaintaining their phases. In another embodiment, the signal combiner 160can invert one of the phases and sum the two signals. In yet anotherembodiment, the signal combiner 160 can generate the sum of the twosignals and can invert the output signal.

The output of the signal combiner 160 represents the output IF signal.The output IF signal can be coupled to an output filter 170 that can be,for example, a low pass filter or bandpass filter that is configured toremove undesired signal products from the IF output signal. The outputfilter 170 can be configured as a fixed bandwidth filter or can beconfigured as a programmable bandwidth filter, where the bandwidth isdetermine, in part, based on a mode of the receiver 100.

The output of the output filter 170 can be coupled to an IF amplifier172 that can be configured to amplify the output. The IF amplifier 172can be a variable gain amplifier. The gain of the IF amplifier 172 canbe controlled using one or more control inputs (not shown) on thereceiver 100. The output of the IF amplifier 172 can be the output ofthe receiver 100.

The receiver 100 can also include a DC offset cancellation module 180configured to substantially remove the DC component on each of thein-phase and quadrature signal paths. DC signals at the inputs to thethird and fourth mixers 152 and 154 result in the generation of LOsignals at the outputs of the respective third and fourth mixers 152 and154. Because the LO signal can represent an undesired signal, thereceiver 100 can incorporate a DC offset cancellation module 180 thatmonitors the DC offset and compensates for it to substantially remove itfrom both the in-phase and quadrature signal paths prior to upconversionto the output IF.

The receiver 100 can also include an I/Q calibration module 184. Thereceiver 100 can reduce the contribution due to undesired signals if thein-phase (I) and quadrature (Q) signal paths can be balanced. The I/Qcalibration module 184 can reduce or substantially eliminate gaindifferences in the I and Q signal paths and can ensure that the I and Qsignal paths are substantially in quadrature.

The I/Q calibration module 184 can be coupled to one or more gain stagesin each of the I and Q signal paths. In the embodiment shown in FIG. 2,the I/Q calibration module 184 is coupled to the filters 132 and 134 inthe I and Q signal paths. The I/Q calibration module 184 can beconfigured to adjust the gain through one or more of the filters inorder to balance the gains of the I and Q signal paths. Additionally,the I/Q calibration module 184 can be configured to adjust the phaseoffset contributed by the first phase shifter 122 in order to maintainthe quadrature nature of the two signal paths.

It may be advantageous to implement the entire receiver 100 on a singleintegrated circuit, such that the processes and conditions used tomanufacture the in-phase and quadrature signal components are closelymatched, resulting in more closely matched I and Q signal paths.Additionally, it may be advantageous to implement the components on asingle IC to minimize path length distances or variations thatcontribute to mismatches. A single IC implementation can also result ina smaller receiver 100 package.

FIG. 3 is a simplified functional block diagram of a receiver 100implementing a digital IF generation module 200. The receiver 100implements some of the functionality in analog domain and otherfunctionality in the digital domain in order to capitalize on variousadvantages of the respective domains. The functional block diagram ofFIG. 3 omits some blocks for the sake of clarity. For example, the RFand IF LOs and their respective phase shifters are not illustrated, norare the DC offset and I/Q calibration modules illustrated.

The RF portion of the receiver 100 embodiment of FIG. 3 is configuredsimilar to that shown and described in FIG. 2. An RF amplifier 102, heredepicted as a variable gain LNA, is configured to receive an inputsignal at a desired RF frequency. The input signal can be within anoperating band of possible input signals and undesired channels withinthe operating band may appear as interference sources.

The output of the RF amplifier 102 is coupled to first and secondmixers, 112 and 114, configured to downconvert I and Q signalcomponents, respectively, to I and Q baseband or low IF signals. Theoutput of the first mixer 112 represents the I baseband or low IFsignal. The signal is coupled to a the in-phase filter 132. The in-phasefilter 132 can be configured to provide at least partial channelselection. The in-phase filter 132 can be configured to provide at leasta portion of the desired channel selectivity. A remaining portion ofchannel selection can be implemented in the digital domain, as will bedescribed below. The in-phase filter 132 can also operate as ananti-aliasing filter to substantially suppress aliased components afterdigitizing the signal.

Similarly, the output of the second mixer 114 represents the quadraturesignal. The quadrature signal is coupled to the quadrature filter 134for partial channel selection and anti-alias filtering. The shape of thein-phase and quadrature filters 132 and 134 can be determined, in part,by the amount of channel selection performed by subsequent digitalfilters. Additionally, the shape of the anti-aliasing filter responsecan be determined in part by the sampling rate of the subsequentdigitizing operation.

The output of the in-phase and quadrature filters, 132 and 134, iscoupled to a digital IF generator 200 configured to digitally filter andupconvert the I and Q signals to a selectable IF. The digital IFgenerator 200 can also be configured to convert the digital IF signal toan analog signal representation. The digital IF generator 200 can thusbe configured to accept analog I and Q signal inputs, digitally filterand upconvert the signals and combine them into a composite digital IFsignal, and convert the digital IF signal to an analog IF signal. Amodule that interfaces with the digital IF generator 200 can becompletely unaware of the digital processing performed by the digital IFgenerator 200.

The digital IF generator 200 includes a first Analog to DigitalConverter (ADC) 202 configured to receive the downconverted in-phasesignal and convert it to a digital representation. The digitizedin-phase signal can be coupled to a first digital filter 212. The firstdigital filter 212 can be configured to perform channel selection on thedigitized in-phase signal. In one embodiment, the first digital filter212 can be configured to provide the desired channel selectivityresponse. In another embodiment, the first digital filter 212 can beconfigured to have a frequency response that operates in conjunctionwith the in-phase filter 132 to produce the desired channel selectivity.

The output of the first digital filter 212 can be coupled to a firstdigital frequency converter 252 configured to frequency convert thefiltered in-phase digital signal to an in-phase digital IF. The outputof the first digital frequency converter 252 is coupled to a first inputof a digital signal combiner 260.

The digital IF generator 200 includes a quadrature signal path that iscomplementary to the in-phase signal path. A second ADC 204 isconfigured to accept the quadrature signal from the quadrature filter134. The second ADC 204 converts the quadrature signal to a digitalrepresentation and couples the digital quadrature signal to a seconddigital filter 214.

The second digital filter 214 filters the digital quadrature signal toprovide the desired channel selectivity. The filtered digital quadraturesignal is coupled to a second digital frequency converter 254 configuredto frequency convert the filtered quadrature digital signal to aquadrature digital IF signal. The output of the second digital frequencyconverter 254 is coupled to a second input of the digital signalcombiner 260.

The first and second digital filters 212 and 214 can be configured withfixed bandwidths or can be configured to have controllable bandwidthsand frequency responses. IN one embodiment, the bandwidths and frequencyresponses of the first and second digital filters 212 and 214 aresubstantially the same. In another embodiment, the first and seconddigital filters 212 and 214 can have distinct bandwidths and frequencyresponses. In some embodiments, the bandwidth and frequency response canbe based in part on an operating mode of the receiver 100. For example,the first and second digital filters 212 and 214 can be configured witha first response if the receiver 100 is configured to process analogNTSC video signals. The first and second digital filters 212 and 214 canbe configured with a second response if the receiver 100 is configuredto process DVB-T signals. The filter responses can be selectivelyprogrammable to any of a plurality of predetermined frequency responses.

In one embodiment, each of the first and second digital filter 212 and214 can be implemented as a digital signal processor (DSP) configured toprovide a filter response based on one or more filter coefficientsstored in a memory (not shown). The first and second digital filters 212and 214 can be configured to store filter coefficients for a pluralityof filter responses, and the DSP can be configured to select acoefficient set based, for example, on a mode or channel configuration.

The first and second digital frequency converters, 252 and 254, can beconfigured to perform frequency conversion according to any one ofvarious frequency conversion techniques. For example, the first andsecond digital frequency converters, 252 and 254, can be configured asmixers, multipliers, rotators, or some other frequency converter.

The digital signal combiner 260 can be configured as a signal summer.Additionally, the digital signal combiner 260 can be configured toinvert one or both of the digital IF signal components. The digitalsignal combiner 260 couples the combined, composite digital IF signal toa digital to analog converter (DAC) 270 configured to convert thedigital IF signal to an analog IF signal. The analog IF signalrepresents the output of the digital IF generator 200.

The analog IF signal is coupled to an output filter 170 and an IFamplifier 172. The output filter 170 can be configured to remove anyundesired frequency conversion products and any undesired signalcomponents generated by the DAC 270.

FIG. 4 is a simplified functional block diagram of an embodiment of areceiver 100 with digital IF generation and I/Q imbalance calibration.The receiver 100 includes a receive signal portion 400 that isconfigured to receive an input signal and convert it to a digital IF. AnI/Q detector 460 is coupled to the output of the receive signal portion400 and is configured to determine the relative phase and amplitude ofthe I and Q signal components during a calibration period. One or morefeedback loops can operate to correct the amplitude and phase balance ofthe I and Q signal paths in order to compensate for any path mismatchesor imbalances.

The receiver 100 is configured to have a signal processing mode and acalibration mode. The operation of the receiver 100 during signalprocessing mode is essentially the same as the receiver embodiment shownin FIG. 3.

An input RF signal is coupled to the RF amplifier 102 at the input ofthe receive signal portion 400 of the receiver 100. The output of the RFamplifier 102 is coupled to a first multiplexer 410 that is configuredto select the RF amplifier 102 output during signal processing mode. Thefirst multiplexer 410 couples the RF amplifier 102 output to first andsecond mixers 112 and 114 to frequency convert the signal to I and Qbaseband or low IF signal components.

An RF LO 420 having a LO generator 422 and phase shifter 424 isconfigured to drive the first and second mixers 112, and 114 within-phase and quadrature LO signals, respectively. The RF LO 420 can beimplemented on the same IC as the receive signal portion 400 or can beconfigured as a distinct module. The downconverted I and Q signals arefiltered in I and Q filters 132 and 134, respectively, before beingdigitally converted and digitally upconverted to the desired IF.

The I signal is digitally converted using a first ADC 202 while the Qsignal is digitally converted in a second ADC 204. The digital I signalis upconverted to a digital in-phase IF signal using a first digitalfrequency converter 252. The digital Q signal is upconverted to adigital quadrature signal using a second frequency converter 254. Asecond LO 440 including an LO generator 442 and phase shifter 444 isused to provide the quadrature LO signals to first and second amplifiers452 and 454 that drive the digital frequency converters 252 and 254. Thesecond LO 440 can be implemented on the same IC or on a module orsubstrate distinct from the receive signal portion 400.

The digital I and Q IF signal components are coupled to the inputs of adigital signal combiner 260 where they are combined into a compositedigital IF output signal. The receive signal portion 400 of the receiver100 is depicted as providing a digital IF output signal. However, thereceiver 100 can include a DAC at the output if an analog IF signal isdesired.

The receiver 100 can be configured to self calibrate in order tocompensate for any imbalances in the I and Q signal paths. The receiver100 can be configured to include an I/Q detector 460 couple to one ormore feedback loops configured to provide correction signals tocompensate for gain and phase imbalances in the I and Q signal paths.

The receiver 100 can perform the calibration process at distinctintervals, such as power up, channel selection, or mode selection. Inanother embodiment, the receiver 100 can be configured to performcalibration on a periodic basis.

During calibration, a calibration tone can be injected into the frontend of the receive signal portion 400. In the embodiment shown in FIG.4, the I and Q outputs of the first LO 420 are coupled to a tonemultiplexer 426. The tone multiplexer 426 is configured to selectbetween the I and Q LO signals and couple the selected tone to a toneamplifier 412 that drives an input of the first multiplexer 410. Thefirst multiplexer 410 is configured to select the tone input duringcalibration mode.

Because the tone injected into the front end of the receive signalportion is generated by the same first LO 420 that is used to generatethe local oscillator signals used in the first frequency conversion, thetone and LO signals are coherent and may differ by only a phase offset.The phase offset can be substantially minimized by minimizing the pathdifferences experienced by the LO signals, or by introducing phasedelays in one or more of the LO paths to equalize the paths.

Thus, during the calibration process, the tone multiplexer 426 can beconfigured to selectively alternate between the in-phase and quadratureLO signals to selectively introduce in-phase and quadrature signals tothe receiver 100 front end. The signal in the receive signal portion 400will be substantially an in-phase signal component during the portion oftime that the tone multiplexer selects the in-phase LO signal.Similarly, the signal in the receive signal portion 400 will besubstantially a quadrature signal component during the portion of timethat the tone multiplexer selects the quadrature LO signal.

When the tone multiplexer 426 selects the in-phase tone, there issubstantially no quadrature signal present in the receive signal portion400. The output of the first and second mixers 112 and 114 are DCsignals representative of the phase and amplitude imbalances in thefront end portion of the receiver 100. The output from the digitalsignal combiner 260 is substantially a signal representative of thephase and amplitude contribution introduced by the complete I and Qsignal processing path.

The output of the digital signal combiner 260 is coupled to an input ofan I/Q detector 460. The I/Q detector 460 includes an in-phase mixer 462and a quadrature mixer 464 that each have one input coupled to thedigital signal combiner 260 output. The LO port of the in-phase mixer462 is driven by the in-phase LO signal from the second LO 440. The LOport of the quadrature mixer 464 is driven by the quadrature LO signalfrom the second LO 440. The outputs of the in-phase mixer 462 andquadrature mixer 464 are coupled to inputs of a signal combiner 466.Therefore, the I/Q detector 460 is configured to generate a DC valuerepresentative of the composite DC offset from the receiver 400. Thecomposite DC offset is representative of the phase and amplitudeimbalance of the receiver 100.

The output of the I/Q detector 460 is coupled to one or more feedbackloops. For example, a first feedback lop can be configured to compensatefor amplitude imbalance while a second feedback loop can be configuredto compensate for phase imbalance. The output of the I/Q detector 460 istypically a DC error signal. The DC error signal is coupled to acalibration loop filter 470 that can be used to adjust the rate that thefeedback loop adjusts the imbalances.

The output of the calibration loop filter 470 can be coupled to anamplifier 472 that can be used to amplify the error signal. In oneembodiment, the amplifier 472 can be implemented as a comparator that isconfigured to toggle between two values depending on whether the DCoffset is greater or less than a predetermined threshold, such as zerovolts. The amplified error signal is coupled to a search module 474,such as a binary search module, that can be configured to determine afeedback value based on a search.

The search module 474 can be configured, for example, to perform abinary search to determine a DC correction value. A binary search usesthe amplifier 472 or comparator output to determine if the nextincrement is to a greater value or a lesser value. The binary search cancontinue until the search converges on a value. For example, if thesearch module 474 is configured to provide a 10-bit digital output, thebinary search can converge in typically 11 or fewer iterations.

The output of the search module 474 is coupled to a multiplexer 476 thatis configured to provide the correction value to either a gain feedbackpath or a phase feedback path. The gain feedback path includes a DAC 482coupled to control the gain of the first and second amplifiers, 452 and454, that drive the digital frequency converters 252 and 254. The phasefeedback path includes a DAC 484 coupled to the digital frequencyconverters 252 and 254 to compensate for phase imbalances.

In one embodiment, the receiver 100 can initiate a calibration mode inwhich the tone multiplexer 426 selects the in-phase signal and couplesthe in-phase signal to the receiver 100 front end. The I/Q detectoroperates on the signal and causes the gain and phase feedback loops toconverge upon values that are applied to the corresponding amplifier 452and digital frequency converter 252. The tone multiplexer 426 can thenbe configured to select the quadrature LO signal and the process can berepeated for the quadrature amplifier 454 and frequency converter 254.

FIG. 5 is a simplified functional block diagram of an embodiment of areceiver 100 having digital IF generation and I/Q imbalance calibration.The receiver 100 of FIG. 5 is similar to the receiver shown in FIG. 4,except that the I/Q imbalance is performed using digital signalprocessing I/Q calibration modules 512 and 514 positioned in series withthe I and Q signal paths.

The receiver 100 is configured to have at least two operating modesincluding a signal processing mode and a calibration mode. The receiver100 operation in the signal processing mode is substantially the same asthat described for the receiver embodiments of FIGS. 3 and 4. Theembodiment of FIG. 5 includes an output DAC 270 and also explicitlydepicts the second LO 442 and phase shifter 444 as implemented in commonwith the signal processing path of the receiver 100.

As was the case with the embodiment shown in FIG. 4, the embodiment ofFIG. 5 includes a first multiplexer 410 configured to select between anRF amplifier 102 output or a tone used during calibration mode. Duringsignal processing mode, the I/Q calibration modules 512 and 514 correctthe respective I and Q signal components by gain and phase compensationvalues determined during the calibration mode.

During calibration mode, the I or Q calibration tone is coupled to thefront end of the receiver 100. The first I/Q calibration module 512 isconfigured to monitor the digital I and Q signal components and isconfigured to adjust the gain and phase offset applied to the in-phasesignal component. Similarly, the second I/Q calibration module 514 isconfigured to monitor the digital I and Q signal components and isconfigured to adjust the gain and phase offset applied to the quadraturesignal component.

FIG. 6 is a simplified flowchart of a method 600 of receiving a signal,such as a television signal that can be an analog television signal or adigital television signal depending on an operating mode. The method 600can be performed by any of the receivers shown in FIGS. 1-5. Of course,the method 600 is not limited to processing of television signals.

The method 600 begins at block 610 where the receiver is provided a modeselect control signal. The mode select signal may indicate the type ofsignal that is to be received, the signal source, an operating frequencyrange, and the like, or some combination of operating parameters. In oneembodiment, the mode selection can indicate whether an analog signal,such as an NTSC television signal, or a digital signal, such as a DVB-Tsignal, is to be processed. The receiver can configure filters andamplifier gains based on the mode selection.

The receiver proceeds to block 620 and receives channel selectioninformation. The receiver can be configured, for example, to receive anindication of an operating frequency band and a frequency of a desiredchannel or a designator of a desired channel.

The receiver proceeds to block 630 and configures the local oscillatorfrequencies based on the mode and channel selection information. Forexample, the receiver can be configured to implement downconversion to alow IF when an NTSC signal is to be received, and may be configured toimplement direct downconversion to a zero-IF or baseband if a digitalsignal is to be received. The receiver may also configure the frequencyof the second LO used for upconversion to the desired IF based on theoperating mode.

After configuring the local oscillator frequencies, the receiverproceeds to block 640 and performs I/Q calibration, if I/Q calibrationis incorporated into the receiver. The receiver can, for example,decouple the input signal from the receiver and introduce one or morecalibration tones and correct for any I/Q imbalance based on thecalibration tones.

After performing I/Q calibration, the receiver can proceed to block 650and quadrature downconvert the desired channel to either a basebandsignal or a low IF signal, depending on the mode selection. The receivermay also perform partial channel selection in order to remove someinterferers and to provide anti-aliasing filtering. The receiverproceeds to block 660 and digitizes the downconverted I and Q signals.

The receiver proceeds to block 670 and digital filters the I and Qsignals. The receiver can be configured to perform channel selection inthe digital domain using a digital filter selected from a plurality ofdigital filter responses based on the mode selection.

The receiver proceeds to block 680 and digitally upconverts the I and Qsignals to the desired IF. The receiver can be configured to generate aLO signal and perform the frequency conversion completely in the digitaldomain. As such, the balance and relationship of the I and Q signals maybe tightly controlled. The receiver can combine the digital I and Q IFsignal components to generate a composite digital IF signal.

The receiver can then proceed to block 690 and convert the digital IFsignal to an analog IF signal for processing and demodulation. Thereceiver can thus interface with legacy processing devices whileincorporating digital IF generation.

A receiver and method of receiving signals are described. A receiver canselectively convert a desired RF channel to a low IF or a basebandsignal using a direct conversion architecture. The receiver can beconfigured to downconvert the desired channel to I and Q signalcomponents. The receiver can perform partial channel selection on thedownconverted I and Q signals. The receiver can digitize the filtered Iand Q signals and can digitally filter each of the digitized I and Qsignals to perform channel selection.

The receiver can digitally upconvert the I and Q signals to an IF. Thereceiver can combine the digital I and Q IF signals to generate acomposite digital IF signal. The receiver can convert the digital IFsignal to an analog IF signal.

The receiver may implement one or more modules that can be configured tocalibrate the receiver signal paths to substantially remove any I and Qimbalance in the signal paths. The modules can include feedback modulesor can be implemented as digital signal processing modules placed inseries with the I and Q signal paths.

The receiver can be implemented on a single IC. Such an implementationallows the various elements to be better matched than is generallypossible using discrete elements or multiple ICs. The ability to closelymatch the elements of the receiver can reduce the level of DC offseterror attributable to element mismatches.

The steps of a method, process, or algorithm described in connectionwith the embodiments disclosed herein may be embodied directly inhardware, in a software module executed by a processor, or in acombination of the two. The various steps or acts in a method or processmay be performed in the order shown, or may be performed in anotherorder. Additionally, one or more process or method steps may be omittedor one or more process or method steps may be added to the methods andprocesses. An additional step, block, or action may be added in thebeginning, end, or intervening existing elements of the methods andprocesses.

The above description of the disclosed embodiments is provided to enableany person of ordinary skill in the art to make or use the disclosure.Various modifications to these embodiments will be readily apparent tothose of ordinary skill in the art, and the generic principles definedherein may be applied to other embodiments without departing from thespirit or scope of the disclosure. Thus, the disclosure is not intendedto be limited to the embodiments shown herein but is to be accorded thewidest scope consistent with the principles and novel features disclosedherein.

1. A receiver comprising: a downconverter configured to downconvert aninput signal to a signal in a first frequency band; an analog to digitalconverter (ADC) coupled to the downconverter and configured to digitizethe signal in the first frequency band to produce a digitalrepresentation of the signal in the first frequency band; and a digitalupconverter configured to upconvert the digital representation of thesignal in the first frequency band to a digital representation of thesignal in a second frequency band.
 2. The receiver of claim 1, whereinthe first frequency band comprises one of a baseband frequency band or alow Intermediate Frequency (IF) band based on a mode of the receiver. 3.The receiver of claim 1, wherein the downconverter comprises: anin-phase downconverter configured to downconvert an in-phase componentof the input signal to the first frequency band; and a quadraturedownconverter configured to downconvert a quadrature component of theinput signal to the first frequency band.
 4. The receiver of claim 1,wherein the downconverter comprises: an in-phase downconverterconfigured to downconvert an in-phase component of the input signal tosubstantially a baseband in-phase signal; and a quadrature downconverterconfigured to downconvert a quadrature component of the input signal tosubstantially a baseband quadrature signal.
 5. The receiver of claim 1,wherein the downconverter comprises: an in-phase downconverterconfigured to downconvert an in-phase component of the input signal to ain-phase low Intermediate Frequency (IF) signal; and a quadraturedownconverter configured to downconvert a quadrature component of theinput signal to a quadrature low IF signal.
 6. The receiver of claim 1,further comprising a filter configured to perform at least partialchannel selection of the signal in the first frequency band prior to theADC.
 7. The receiver of claim 1, further comprising a digital filterconfigured to perform channel selection of the digital representation ofthe signal in the first frequency band.
 8. The receiver of claim 1,wherein the digital upconverter comprises: a first digital upconverterconfigured to digitally upconvert an in-phase component of the inputsignal to an in-phase digital signal at a desired Intermediate Frequency(IF); and a second digital upconverter configured to digitally upconverta quadrature component of the input signal to a quadrature digitalsignal at the desired IF.
 9. The receiver of claim 8, further comprisinga digital signal combiner configured to combine the in-phase digitalsignal at the desired IF with the quadrature digital signal at thedesired IF.
 10. A receiver comprising: a first frequency converterconfigured to downconvert a received signal to an in-phase basebandsignal component; a second frequency converter configured to downconvertthe received signal to a quadrature baseband signal component; a firstanalog filter coupled to the first frequency converter and configured toperform at least partial channel selection on the in-phase basebandsignal component; a second analog filter coupled to the second frequencyconverter and configured to perform at least partial channel selectionon the quadrature baseband signal component; a first Analog to DigitalConverter (ADC) coupled to the first analog filter and configured toconvert the in-phase baseband signal component to a digital in-phasebaseband signal component; a second ADC coupled to the second analogfilter and configured to convert the quadrature baseband signalcomponent to a digital quadrature baseband signal component; a firstdigital filter coupled to the first ADC and configured to digitallyfilter the digital in-phase baseband signal component to generate adigitally filtered in-phase baseband signal component; a second digitalfilter coupled to the second ADC and configured to digitally filter thedigital quadrature baseband signal component to generate a digitallyfiltered quadrature baseband signal component; a first digitalupconverter configured to digitally upconvert the digitally filteredin-phase baseband signal component to an in-phase Intermediate Frequency(IF) signal component at a desired IF; a second digital upconverterconfigured to digitally upconvert the digitally filtered quadraturebaseband signal component to a quadrature IF signal component at thedesired IF; and a digital signal combiner configured to combine thein-phase IF signal component with the quadrature IF signal component.11. A method of receiving a signal, the method comprising: frequencyconverting an input signal to an intermediate signal in a firstfrequency band; digitizing the intermediate signal; and digitallyconverting the intermediate signal to a second frequency band.
 12. Themethod of claim 11, wherein frequency converting the input signalcomprises: downconverting the input signal to an in-phase basebandsignal component; and downconverting the input signal to a quadraturebaseband signal component.
 13. The method of claim 11, wherein theintermediate signal comprises: an in-phase baseband signal component;and a quadrature baseband signal component.
 14. The method of claim 11,further comprising performing partial channel selection on theintermediate signal.
 15. The method of claim 11, wherein digitizing theintermediate signal comprises: digitizing an in-phase signal componentof the intermediate signal; and digitizing a quadrature signal componentof the intermediate signal.
 16. The method of claim 11, whereindigitally converting the intermediate signal comprises: digitallyupconverting an in-phase signal component of the intermediate signal toan in-phase Intermediate Frequency (IF) component at a desired IF;digitally upconverting a quadrature signal component of the intermediatesignal to a quadrature IF component at the desired IF; and combining thein-phase IF component with the quadrature IF component.
 17. A method ofcalibrating a quadrature receiver, the method comprising: injecting acalibration tone to a signal path of a quadrature receiver; detecting anamplitude and phase imbalance of the quadrature receiver; adjusting again of at least one of an in-phase and a quadrature signal path basedon the amplitude imbalance; and adjusting a phase of at least one of thein-phase and quadrature signal paths based on the phase imbalance. 18.The method of claim 17, wherein injecting the calibration tone comprisesinjecting one of a quadrature or an in-phase Local Oscillator (LO)signal to the signal path.
 19. The method of claim 18, wherein the oneof the quadrature or in-phase LO signal is synchronized with a LO signalused to downconvert the calibration tone to a DC signal.
 20. The methodof claim 17, wherein detecting the amplitude and phase imbalance of thequadrature receiver comprises: downconverting an in-phase IntermediateFrequency (IF) signal component to a first DC signal; downconverting aquadrature IF signal component to a second DC signal; combining thefirst and second DC signals to generate a combined DC signal; anddetermining the phase imbalance based on the combined DC signal.
 21. Aquadrature receiver calibration apparatus, the apparatus comprising: atone generator configured to generate a calibration tone; a couplerconfigured to couple the calibration tone to a signal path of thequadrature receiver; a detector configured to detect an in-phase andquadrature signal component when the calibration tone is coupled to thesignal path; a gain feedback module configured to adjust a gain of atleast one of an in-phase signal path and a quadrature signal path; and aphase feedback module configured to adjust a phase of at least one ofthe in-phase signal path and the quadrature signal path.